The present invention relates to a semiconductor integrated circuit device including an ECL (Emitter Coupled Logic).
In semiconductor integrated circuit devices such as ECL (or CML: Current Mode Logic), it is well known in the art, as shown by Japanese Patent Laid-Open No. 134780/1975, that the logic amplitude of an inside ECL circuit is made smaller than that of an outside one in order to speed up the internal operation and reduce the power consumption of the semiconductor integrated circuit device. This type of inside ECL semiconductor integrated circuit device includes an output circuit which is constructed of a logic circuit which exists in the prior art and which is made operative with a normal logic amplitude. As a result, the output circuit allows its output signal to have its operating margin enlarged when the output signal is fed out to external wirings outside of the integrated circuit which have a high noise induction or the like. On the contrary, an inside ECL circuit constructed inside of the integrated circuit is constructed of a minor amplitude ECL circuit so as to ensure the aforementioned speed-up and reduction in the power consumption because it is hardly influenced by the above-described noises or the like.
In the semiconductor integrated circuit thus far described, the inside ECL circuit is made to have its low signal level set at a relatively high level. Accordingly, the integrated circuit device is equipped with an input circuit for receiving an external input signal having a normal level and for shifting the low level of this signal toward the high level.
The input circuit is made to have a construction similar to that of a typical ECL circuit. Therefore, it will have a threshold voltage when it is supplied with a suitable reference voltage which is proper for the external input signal. Moreover, the input circuit solves the following problems which are caused when the external input signal is fed directly to the inside ECL circuit.
Specifically, the inside ECL circuit has its logic threshold voltage set at a relatively high level. Accordingly, the difference between the high level of the external input signal and the logic threshold voltage of the inside ECL circuit is made relatively small. On the other hand, the difference between the low level of the external input signal and the logic threshold voltage is made large. As a result, both the response time of the inside ECL circuit when the external input signal is changed from the high level to the low level and the response time of the inside ECL circuit when the external input signal is changed from the low level to the high level are varied. Moreover, since the difference between the high level of the external input signal and the threshold voltage of the inside ECL circuit is so small, the noise margin of the circuit device is reduced. This problem concerning the noise margin is considered serious because, generally, a relatively large amount of noise is imparted to the outside wirings for feeding the external input signal therethrough.
The input circuit can solve the above problem by having its threshold voltage set at a proper level. However, this input circuit itself establishes a relatively large signal delay. Therefore, it becomes difficult to shorten the overall response time of the integrated circuit device.
In order to solve this new problem which is brought about by the provision of the input circuit typically used for inside ECL circuits, the inventors have examined an inside ECL circuit which has such a relatively low logic threshold voltage that the external input signal may be fed directly to the minor amplitude inside ECL circuit without using such an input circuit. In this case, however, the number of circuit elements in each minor amplitude inside ECL circuit is increased, as will be explained in the following discussion. This results in the integration of the integrated circuit being deteriorated. Especially in a large scale integration device having several thousands gates of the ECLs in one chip, the deterioration in the integration leads to a remarkable increase in the occupied area on the chip, thereby causing a serious disadvantage.
FIG. 1 is a block diagram showing, by two-dotted chain lines, such as ECL integrated circuit (i.e., ECL LSI) which is constructed without incorporating an input circuit. In addition to minor amplitude ECL circuits ECL.sub.1 to ECL.sub.n, there are provided output circuits OB.sub.1 to OB.sub.l for enlarging the logic amplitudes of the inside ECL circuits to a normal logic amplitude. The minor amplitude inside ECL circuits can be formed by a circuit such as shown in FIG. 2A. In this circuit, the ratios R.sub.CN /R.sub.E and R.sub.CO /R.sub.E of a pair of load resistances, which are connected to the respective collectors of paired differential transistors Q.sub.3 and Q.sub.4 constructing the ECL circuit to a constant-current resistance R.sub.E connected to the common emitter of the paired differential transistors, are set at a lower level than is done in the case of a normal ECL circuit.
By those settings of the resistance ratios, the constant current which flows through the aforementioned collector resistance R.sub.CN or R.sub.CO is set at a relatively low level. As a result, the voltage drop at the load resistance R.sub.CN or R.sub.CO by this constant current is relatively reduced so that an output signal V.sub.out has its low level shifted toward the high level. As a result, the output signal V.sub.out or V.sub.out can have its amplitude made smaller than that of an input signal V.sub.in.
Moreover, the circuit under consideration is especially provided with a level shifting resistance R.sub.l. This level shifting resistance R.sub.l is required, as will be described hereinafter, for making the center level of the minor amplitude output signal V.sub.out substantially equal to that of the normal amplitude input signal V.sub.in.
FIG. 2B is a diagram illustrating the input/output transmitting characteristics of the ECL circuit of FIG. 2A.
In this figure, the input/output transmission characteristic curve V.sub.co indicates the relationship for FIG. 2A between the normal amplitude input signal V.sub.in and the collector voltage V.sub.co of the transistor Q.sub.4. The input/output transmission characteristic curve V.sub.co ' illustrates that when the level shifting resistance R.sub.l is not employed, the collector voltage V.sub.co of the aforementioned transistor Q.sub.4 is shifted toward the high level side until it takes the value V.sub.co '. The input/output transmission characteristic curve V.sub.out indicates the relationship for FIG. 2A between the normal amplitude input signal V.sub.in and the minor amplitude output signal V.sub.out. Finally, the input/output transmission characteristic curve V.sub.out ' illustrates that when the level shifting resistance R.sub.l is not employed, the minor amplitude output signal V.sub.out is shifted toward the high level side until it takes the value V.sub.out '.
From these curves it can be seen that by providing the level shifting resistance R.sub.l the output signal of the ECL circuit can be shifted toward the low level side by the voltage drop (e.g., 0.1 V) at that resistance R.sub.l. For example, the minor amplitude output signal V.sub.out has its high output level shifted from V.sub.out (H)' (-0.9 V) to V.sub.out (H) (-1.0 V) and its low output level from V.sub.out (L)' (-1.5 V) to V.sub.out (L) (-1.6 V).
As a result, the center level V.sub.tho of the output signal V.sub.out can be deduced from the following Equation (1): ##EQU1## Thus, the minor amplitude output signal V.sub.out can have its center level V.sub.tho (-1.3) made substantially equal to the center level V.sub.thi (i.e., a logic threshold voltage: e.g., -1.32 V) of the normal amplitude input signal V.sub.in.
In this case, however, a problem arises in that the integration of the integrated circuit is lowered because each minor amplitude inside ECL circuit requires a level shifting resistance R.sub.l, as has been described in the above. Also, another disadvantage is created because useless power is consumed by the aforementioned level shifting resistance R.sub.l. This, of course, undesirably increases the overall power consumption of the circuit.
Thus, it can be seen that in an ECL integrated circuit device (ECL LSI) having a lower internal logic amplitude than an external logic amplitude, as has been described hereinbefore, it is preferable to have a special input circuit for receiving the input signal of the former separate from the minor amplitude inside ECL circuit to avoid the above disadvantages. However, the experiments of the inventors have revealed that the transmission delay time of that input circuit is innegligibly high in comparison with the time required for the logic operations in the ECL LSI, and that, because of this, the overall operating speed of this ECL LSI is considerably restricted.
For example, when the input circuit is constructed of the normal ECL circuit, as has been described in the foregoing Japanese Patent Laid-Open No. 34780/1975, its transmission delay time is about 0.3 nanosecs.
On the other hand, the transmission delay time of the minor amplitude inside ECL circuit for one gate is about 0.35 to 0.8 nanosecs. About four gates are connected in cascade to perform one logic operation. Therefore, the time necessary for the logic operation inside of the LSI is about 1.4 (i.e., 0.35.times.4=1.4) nanosecs at the minimum.
In the worst case, therefore, the time (e.g., 0.3 nanosecs) required by the input circuit reaches a value as high as 21 (0.3/1.4.perspectiveto.0.21) % of the time (e.g., 1.4 nanosecs) necessary for the actual logic operation.
Therefore, the reduction in the transmission delay time of that input circuit is very important for the improvement in the operating speed of the ECL LSI as a whole.